Phase-locked loop (PLL) frequency synthesizers are commonly used in radio frequency transmitter and receiver circuits to produce a stable, precise, and selectably variable frequency source. A typical single loop PLL synthesizer includes a divided down stable reference frequency source, a voltage controlled oscillator (VCO) for producing an output signal having a controlled frequency, a frequency divider for dividing down the VCO output, a phase comparator for detecting the phase difference between the two divided down frequencies of the VCO and stable reference source, and for producing an error signal for representing the detected phase differences, and a loop filter for filtering the error signal and coupling it to the VCO to adjust the synthesizer's output frequency. The loop filter following the phase comparator is needed to reduce spurious frequency modulation of the VCO output produced by harmonics of the final comparison frequency and by the noise generated from the dividers in the phase detector. The divided down frequencies of the VCO and the stable reference source are phase-compared in the phase comparator. The output of the comparator is low-pass filtered in a loop filter and used to control the frequency of a VCO in order to lock the VCO output frequency to the reference source.
For this type of single loop PLL configuration, the relationship between the VCO output frequency, F.sub.vco, and the reference source, F.sub.ref, is given by the following equation: EQU F.sub.vco =M/N.times.F.sub.ref
where M and N are the divider ratios of the respective frequency dividers.
It is also known to utilize an adjustable bandwidth type loop filter in frequency synthesizers to shorten the phase-lock frequency acquisition time and provide a more stable output signal. This is typically accomplished by switching a "lag filter" network in-to or out-of the loop filter circuit. Exemplary prior art configurations of this sort are disclosed in the following U.S. Pat. Nos.:
4,516,083 - Turney (1985) PA1 4,524,333 - Iwata et al (1985) PA1 4,559,505 - Suarez et al (1985) PA1 4,714,899 - Kurtzman et al (1987) PA1 4,980,653 - Shepard (1990) PA1 4,525,686 - Yokoya (1985) PA1 4,745,371 - Haine (1988) PA1 4,885,553 - Hietala et al (1989) PA1 4,937,538 - Hovens (1990) PA1 4,980,652 - Tarosawa et al (1990) PA1 4,484,358 - Iwahashi (1984) PA1 4,336,616 - Carson et al (1982) PA1 4,912,434 - Wyatt (1990) PA1 4,135,165 - Coe (1979) PA1 4,167,711 - Smoot (1979) PA1 4,587,496 - Wolaver (1986)
In a scanning receiver, the frequency synthesizer is constantly reprogrammed to tune to a particular channel and to remain tuned to that channel if it is active, but otherwise, to proceed to the next channel or return to a home channel. It is desirable to accomplish this frequency hopping or scanning in as short a time as possible, therefore, necessitating rapid settling of the synthesizer output frequency. Moreover, to accommodate fast frequency changes, it is also desirable that the loop filter of the PLL frequency synthesizer initially have a wide bandwidth for quick acquisition of a desired frequency. Once frequency lock has been obtained, a PLL having a narrow bandwidth is desirable to attenuate noise and reference signal feed through. However, there are certain practical problems encountered in switching from a wide to narrow loop bandwidth. These have to do with the imperfections of the C-MOS switches commonly used in the loop lag filter to accomplish the bandwidth switching.
Typically, C-MOS switches gives rise to feed-through transients imparted to the switched output by the control inputs and, introduce voltage transients that result in undesirable noise on the synthesizer output signal. These transients are especially bothersome when switching directly from the wide to a narrow bandwidth because the loop is then sluggish, and any disturbances at the output of the loop filter take an unacceptably long time to be regulated out. To reduce frequency disturbances caused by voltage transients during bandwidth switching, prior art PLL frequency synthesizers, such as described in U.S. Pat. No. 4,752,749 to Mayer (1988), neutralize or eliminate voltage differences across the output capacitor of the loop filter and the input to the VCO. In a similar approach, disclosed in U.S. Pat. No. 4,546,329 to Unger (1985), a transmission gate couples a resistance between the lag filter capacitors and signal ground to reduce transients during bandwidth switching. Other analogous prior art solutions to the switching transient problems are exemplified by U.S. Pat. Nos. 4,007,429 to Cadalora et al (1977) and 4,167,711 to Smoot (1979).
Although these prior art schemes reduce the effect of switching transients, they are complex, expensive to implement, and do not adequately eliminate transient generated instabilities. Moreover, whenever switching from the wide to the narrow bandwidth occurs, an extended duration transient is generated if the VCO is not exactly on frequency. It is advisable to reduce the system bandwidth initially only to the extent necessary for proper noise squelch operation (i.e, to get rid of comparison frequency harmonics). Once a useful signal is received, the bandwidth can be further reduced for normal (single channel) receiver operation. The present invention overcomes these inadequacies of the prior art solutions by providing a loop lag filter that has one or more intermediate bandwidths, and wherein the switching transients and any frequency kicks associated with switching between bandwidth modes is eliminated.
Briefly described, the present invention provides an improved loop lag filter for frequency synthesizers. As part of a synthesizer loop filter, the improved loop lag filter network includes a resistance which is controllably added into the filter by the use of a C-MOS switch during the wide bandwidth "acquisition" mode of the synthesizer's operation. This results in a change in the transfer function of the lag filter and a narrowing of its bandwidth to provide an intermediate bandwidth mode of operation. By first switching to an intermediate bandwidth, as opposed to switching directly to a narrow bandwidth, the magnitude and duration of any switching transients generated are considerably reduced. However, a short duration switching transient is still generated when the bandwidth is finally switched from the intermediate mode to its narrowest or "capture" mode. Although reduced, such a transient may be especially troublesome, if the VCO is frequency modulated with low-frequency, low-deviation tone or data, as is typical in tone squelch applications. Accordingly, the present invention provides a solution to this problem by incorporating an additional capacitor in the filter at the output terminal of the C-MOS switch (i.e., at the output of the switch that is used to add the resistance into the filter), to provide a low impedance path to signal ground. This capacitor combined with the voltage divider action provided by other resistors in the lag filter results in an almost total elimination of any frequency kick associated with bandwidth switching.